This invention relates to a programmable interface for peripheral circuit cards in computer systems, particularly personal computer systems. More particularly, this invention relates to such an interface using special-purpose programmable logic devices to enable a designer of peripheral circuit cards to customize the interface to the computer bus for a particular card design.
Computer systems, particularly personal computer systems, typically include (a) a central processor unit which, in the case of a personal computer, is a microprocessor; (b) a main circuit board, including the central processor unit, memory devices and other essential circuits; (c) mass storage devices such as disk drives and associated controller circuits; (d) one or more ports for communication with peripheral devices; and, optionally, (e) one or more printed circuit cards for performing various optional functions, such as additional memory, graphics, communication or storage resources and control. These printed circuit cards will hereafter be referred to as "peripheral circuit cards".
The central processor unit, memory devices, mass storage devices, ports and peripheral circuit cards all communicate with one another over a communications bus under a particular protocol defined by the bus architecture. This communications bus is termed the system bus. This system bus typically will include address, data, control and arbitration control lines. The arbitration control lines allow devices other than the central processor unit to gain control of the bus. In this manner, these devices, termed bus masters, may control the transfer of data across the bus. By asserting appropriate address and control signals on the bus, the central processor unit or other bus master can transfer data from one device or card to another as needed, e.g., from mass storage device to main memory. On such a bus, each device must have a unique address to allow the unique selection of data sources and destinations. Bus conflicts result if addresses are not unique--e.g., two or more devices attempting to transfer data to or from the bus at once.
A representative bus is described in "Micro Channel.RTM. Architecture Specification" and "IBM.RTM. Personal System/2.RTM. Seminar Proceedings", both available from International Business Machines Corporation. To interface to the described bus, a peripheral circuit card must:
1. Provide an 8-, 16- or 32-bit data interface between the bus and integrated circuits on the card. This is typically implemented by bidirectional, tristatable buffers. PA1 2. Provide an address interface between the bus and integrated circuits on the peripheral circuit card. This typically takes the form of address latches for low-order address lines and the generation of a chip select signal for each of the integrated circuits on the card. The chip select signal is the result of decoding highorder address lines which define the block of addresses a given chip will respond to. PA1 3. Provide a control interface which receives timing and control signals from the bus and generates appropriate control signals for the various integrated circuits on the card to coordinate data transfers. In addition, the control interface generates necessary data transfer handshake lines to insure synchronization with the bus. PA1 4. Optionally, provide an arbitration interface to request use of the bus for data transfers not controlled by the central processor unit. This arbitration interface must obey the bus arbitration protocol established for the bus, including specified resolution of arbitration priorities when multiple peripheral circuit cards request use of the bus simultaneously.
In addition, in the protocol used with the described bus, the system bus is used to initialize the peripheral circuit cards when the system is powered up. This initialization includes the assignment of unique, conflict-free addresses to each card and the configuration of specific card functions.
In order to accomplish this, each peripheral circuit card designed for this bus must have a 16-bit card identification number which is readable by the central processor unit. This card identification number is unique to a particular peripheral card design. It must be stored on the card in a non-volatile manner; that is, when system power is removed, the identication number must be retained for use on subsequent system power-up. When the system is powered up, the central processor unit reads the card identification number for each peripheral circuit card present. It then reads a configuration file stored on the system disk drive associated with the peripheral circuit card identification number detected. The configuration file includes a list of alternative addresses by which the peripheral circuit card can be addressed.
The configuration file also specifies data patterns to be written into special configuration registers on the peripheral circuit card to enable each of the available address ranges. The central processor unit can therefore control the addresses to which each peripheral circuit card responds by writing the appropriate values into the configuration registers. By this means, the central processor unit can eliminate address conflicts between peripheral circuit cards by choosing appropriate, non-conflicting addresses for each card during initialization.
The configuration registers may also be used as software-controlled ports to control specific functions on the peripheral circuit card. In this manner, the central processor unit may control specific system hardware functions. Two of the bits in these registers are specified in the bus specification. One of these bits acts as a peripheral circuit card enable bit--i.e., until this bit is written to a logical "1" by the central processor unit, the peripheral circuit card will remain inactive. Another of these bits acts as a non-maskable interrupt flag, which can be written by the central processor unit with a logical "0" to clear an interrupt condition. Remaining bits in the four 8-bit configuration registers can be used for address selection as described above, or for whatever configuration functions are deemed necessary by the card designer. A given card design will not generally require the use of all remaining register bits, and different card designs may in fact require different sets of register bits.
When a peripheral circuit card is designed and manufactured, the available addresses on the card and the chips to which they correspond can be programmed directly into memory or logic devices in a customized interface on the peripheral circuit card. The contents of selected configuration register bit locations may then be logically decoded and used to enable the various address ranges. However, until a card design is finalized, or until manufacturing volumes reach a critical threshold, it may not be cost-effective to design a customized interface to implement the address assignment and chip select decoding functions.
It would be desirable to be able to provide a programmable interface which can be customized by a user for a particular peripheral circuit card design.
It would also be desirable to make features such as peripheral card identification, chip select address decode ranges, latching of chip selects, chip select/feedback "OR"ing, register bit patterns which enable address range selections, and register/pin connections programmable in a non-volatile fashion. Non-volatile programming of these features would allow the programmable interface to retain the particular characteristics required in a given peripheral circuit card design even when power is removed from the peripheral circuit card and the associated computer system.